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1. general description the pca9846 is an ultra-low voltage, quad bi directional translating switch controlled via the i 2 c-bus. the scl/sda upstream pair fans ou t to four downstream pairs, or channels. any or all scx/sdx channels can be selected , determined by the programmable control register. this feature allows mu ltiple devices with the same i 2 c-bus address to reside on the same bus. the switch device can also separate a heavily loaded i 2 c-bus into separate bus segments, eliminating the need for a bus buffer. an active low reset input allows the pca9846 to recover from a situation where one of the downstream i 2 c-buses is stuck in a lo w state. pulling the reset pin low resets the i 2 c-bus state machine and deselects all the channels, as does the internal power-on reset (por) function. the pass gates of the switches are constructed such that the v dd1 pin is used to limit the maximum high voltage which is passed by the pca9846. this allows the use of different bus voltages on each channel, so that 0.8 v, 1.8 v, 2.5 v or 3.3 v parts can communicate without any additional protection. external pull- up resistors pull the bus up to the desired voltage level for each channel. all i/o pins are 3.6 v tolerant. 2. features and benefits ? ultra-low voltage operation, down to 0.8 v to interface with next-generation cpus ? 1-of-4 bidirectional translating switch ? fm+ i 2 c-bus interface logic; comp atible with smbus standards ? active low reset input ? 2 address pins allowing up to 16 devices on the i 2 c-bus ? channel selection via i 2 c-bus ? power-up with all switch channels deselected ? low r on switches ? allows voltage level translation between 0.8 v, 1.8 v, 2.5 v and 3.3 v buses ? reset via i 2 c-bus software command ? i 2 c device id function ? no glitch on power-up ? supports hot insertion since all channels are de-selected at power-on ? low standby current pca9846 4-channel ultra-low voltage, fm+ i 2 c-bus switch with reset rev. 1 ? 9 november 2015 product data sheet
pca9846 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015. all rights res erved. product data sheet rev. 1 ? 9 november 2015 2 of 32 nxp semiconductors pca9846 4-channel ultra-low voltage, fm+ i 2 c-bus switch with reset ? 3.6 v tolerant inputs ? 0 hz to 1 mhz clock frequency ? esd protection exceeds 6000 v hbm per jesd22-a114 and 1000 v cdm per jesd22-c101 ? latch-up testing is done to jedec standard jesd78 which exceeds 100 ma ? two packages offered: tssop16 and hvqfn16 3. ordering information [1] package is in development. contact nxp for availability. 3.1 ordering options [1] package is in development. contact nxp for availability. table 1. ordering information type number topside marking package name description version pca9846bs [1] 846 hvqfn16 plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 4 ? 4 ? 0.85 mm sot629-1 PCA9846PW p9846pw tssop16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 table 2. ordering options type number orderable part number package packing method minimum order quantity temperature range pca9846bs [1] pca9846bsj hvqfn16 reel 13? q1/t1 *standard mark smd 6000 t amb = ? 40 ? cto+85 ?c PCA9846PW PCA9846PWj t ssop16 reel 13? q1/t1 *standard mark smd 2500 t amb = ? 40 ? cto+85 ?c PCA9846PW PCA9846PWz t ssop16 reel 13? q1/t1 *standard mark smd 500 t amb = ? 40 ? cto+85 ?c
pca9846 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015. all rights res erved. product data sheet rev. 1 ? 9 november 2015 3 of 32 nxp semiconductors pca9846 4-channel ultra-low voltage, fm+ i 2 c-bus switch with reset 4. block diagram fig 1. block diagram of pca9846 switch control logic pca9846 reset circuit aaa-017304 sc0 sc1 sc2 sc3 sd0 sd1 sd2 sd3 v ss v dd2 v dd1 reset i 2 c-bus control input filter scl sda a0 a1
pca9846 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015. all rights res erved. product data sheet rev. 1 ? 9 november 2015 4 of 32 nxp semiconductors pca9846 4-channel ultra-low voltage, fm+ i 2 c-bus switch with reset 5. pinning information 5.1 pinning 5.2 pin description [1] hvqfn16 package die supply ground is connected to both the v ss pin and the exposed center pad. the v ss pin must be connected to supply ground for proper device operation. for enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the printed-circuit board in the thermal pad region. fig 2. pin configuration for tssop16 fig 3. pin configuration for hvqfn16 PCA9846PW v dd1 v dd2 a0 sda reset scl sd0 a1 sc0 sc3 sd1 sd3 sc1 sc2 v ss sd2 aaa-017305 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 aaa-017306 transparent top view sd1 sd3 sc0 sc3 sd0 a1 reset scl sc1 v ss sd2 sc2 a0 v dd1 v dd2 sda 4 9 3 10 2 11 1 12 5 6 7 8 16 15 14 13 terminal 1 index area pca9846abs table 3. pin description symbol pin description tssop16 hvqfn16 v dd1 1 15 logic level power supply a0 2 16 address input 0 reset 3 1 active low reset input sd0 4 2 serial data 0 sc0 5 3 serial clock 0 sd1 6 4 serial data 1 sc1 7 5 serial clock 1 v ss 86 [1] supply ground sd2 9 7 serial data 2 sc2 10 8 serial clock 2 sd3 11 9 serial data 3 sc3 12 10 serial clock 3 a1 13 11 address input 1 scl 14 12 serial clock line sda 15 13 serial data line v dd2 16 14 core logic power supply
pca9846 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015. all rights res erved. product data sheet rev. 1 ? 9 november 2015 5 of 32 nxp semiconductors pca9846 4-channel ultra-low voltage, fm+ i 2 c-bus switch with reset 6. functional description refer to figure 1 ? block diagram of pca9846 ? . 6.1 device address following a start condition, the bus master must output the address of the slave it is accessing. the address of the pca9846 is shown in figure 4 . the device pins a0 and a1 must be connected to a valid l ogic signal ? high, low, scl or sda ? to ensure a valid slave address, since no internal pull-up resistors are provided. see table 4 . fig 4. slave address aaa-011933 1 x 1 x x x x r/w x = programmable by hardware
pca9846 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015. all rights res erved. product data sheet rev. 1 ? 9 november 2015 6 of 32 nxp semiconductors pca9846 4-channel ultra-low voltage, fm+ i 2 c-bus switch with reset 6.2 software reset general ca ll, and device id addresses two other different addresses can be sent to the device. ? general call address: allows to reset the device through the i 2 c-bus upon reception of the right i 2 c-bus sequence. see section 6.2.1 ? software reset ? for more information. ? device id address: allows to read id information from the device (manufacturer, part identification, revision). see section 6.2.2 ? device id ( pca9846 id field) ? for more information. table 4. address selection pca9846 address pins 8-bit i 2 c-bus address slave address/bit pattern master must send a1 a0 a7 a6 a5 a4 a3 a2 a1 a0 - r/w 0scl0xe0h 1110000 0/1 0 0 0xe2h 1110001 0/1 0sda0xe4h 1110010 0/1 0 1 0xe6h 1110011 0/1 1scl0xe8h 1110100 0/1 1 0 0xeah1110101 0/1 1sda0xech1110110 0/1 1 1 0xeeh1110111 0/1 sclscl0xb0h 1011000 0/1 scl0 0xb2h 1011001 0/1 sclsda0xb4h 1011010 0/1 scl1 0xb6h 1011011 0/1 sdascl0xb8h 1011100 0/1 sda0 0xbah1011101 0/1 sdasda0xbch1011110 0/1 sda1 0xbeh1011111 0/1 fig 5. general call address fig 6. device id address 0 002aac115 0 0 0 0 0 0 0 r/w r/w 002aac116 1 1 1 1 1 0 0
pca9846 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015. all rights res erved. product data sheet rev. 1 ? 9 november 2015 7 of 32 nxp semiconductors pca9846 4-channel ultra-low voltage, fm+ i 2 c-bus switch with reset 6.2.1 software reset the software reset call allows all the devices in the i 2 c-bus to be reset to the power-up state value through a specific formatted i 2 c-bus command. to be pe rformed correctly, it implies that the i 2 c-bus is functional and that there is no device hanging the bus. the software reset sequence is defined as following: 1. a start command is sent by the i 2 c-bus master. 2. the reserved general call i 2 c-bus address ?0000 000? with the r/w bit set to 0 (write) is sent by the i 2 c-bus master. 3. the device acknowledges after seeing the general call address ?0000 0000? (00h) only. if the r/w bit is set to 1 (read), no acknowledge is returned to the i 2 c-bus master. 4. once the general call address has been sent and acknowledged, the master sends 1 byte. the value of the byte must be equal to 06h. a. the device acknowledges this value only. if the byte is not equal to 06h, the device does not acknowledge it. if more than 1 byte of data is sent, the device does not acknowledge any more. 5. once the right byte has been sent and correctly acknowledged, the master sends a stop command to end the software reset sequence: the device then resets to the default value (power-up value) and is ready to be addressed again within the specified bus free time. if the master sends a repeat ed start instead, no reset is performed. the i 2 c-bus master must interpret a non-acknowledge from the device (at any time) as a ?software reset abort?. the device does not initiate a reset of its registers. the unique sequence that initiates a software reset is described in figure 7 . fig 7. software reset sequence aaa-017308 0 0 0 0 0 0 0 a s 0 swrst call i 2 c-bus address start condition r/w acknowledge from slave(s) 0 0 0 0 1 1 0 0 swrst data = 06h a acknowledge from slave(s) p pca9846 is reset. registers are set to default power-up values.
pca9846 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015. all rights res erved. product data sheet rev. 1 ? 9 november 2015 8 of 32 nxp semiconductors pca9846 4-channel ultra-low voltage, fm+ i 2 c-bus switch with reset 6.2.2 device id (pca9846 id field) the device id field is a 3-byte read-only (2 4 bits) word giving the following information: ? 12 bits with the manufacturer name, unique per manufacturer (for example, nxp). ? 9 bits with the part identification, assigned by manufacturer. ? 3 bits with the die revision, assigned by manufacturer (for example, rev x). the device id is read-only, hardwired in the device and can be accessed as follows: 1. start command 2. the master sends the reserved device id i 2 c-bus address followed by the r/w bit set to 0 (write): ?1111 1000?. 3. the master sends the i 2 c-bus slave address of the slave device it needs to identify. the lsb is a ?don?t care? value. only one device must acknowledge this byte (the one that has the i 2 c-bus slave address). 4. the master sends a re-start command. remark: a stop command followed by a star t command will reset the slave state machine and the device id read cannot be performed. also, a stop command or a re-start command followed by an access to another slave de vice will reset the slave state machine and the device id read cannot be performed. 5. the master sends the reserved device id i 2 c-bus address followed by the r/w bit set to 1 (read): ?1111 1001?. 6. the device id read can be done, starting with the 12 manufacturer bits (first byte + 4 msb of the second byte), followed by the 9 part identification bits (4 lsbs of the second byte + 5 msbs of the third byte), and then the 3 die revision bits (3 lsbs of the third byte). 7. the master ends the reading sequence by nacking the last byte, thus resetting the slave device state machine and allowing the master to send the stop command. remark: the reading of the device id can be stopped anytime by sending a nack command. if the master continues to ack the bytes afte r the third byte, the slave rolls back to the first byte and keeps sending the device id sequence until a nack has been detected. for the pca9846, the de vice id is shown in figure 8 . fig 8. pca9846 device id field 0 aaa-017527 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 revision 1 0 0 0 0 part identification manufacturer
pca9846 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015. all rights res erved. product data sheet rev. 1 ? 9 november 2015 9 of 32 nxp semiconductors pca9846 4-channel ultra-low voltage, fm+ i 2 c-bus switch with reset 6.3 control register following the successful acknowledgement of the slave address, the bus master will send a byte to the pca9846, which will be stored in the control register. if multiple bytes are received by the pca9846, it will save the last byte received. this register can be written and read via the i 2 c-bus. if more than 3 bytes are read, the slave device loops back to the first byte (manufac turer byte) and keeps sending data until t he master generates a ?no acknowledge?. fig 9. device id field read operation aaa-011781 a7 a6 a5 a4 a3 a2 a1 i 2 c-bus slave address of the device to be identified a no acknowledge from master p stop condition m 11 m 10 m9 m8 m7 m6 m5 m4 sr repeated start condition 1 a r/w s 1 1 1 1 1 0 0 device id address start condition 0 a r/w acknowledge from one or several slaves 0 a dont care acknowledge from slave to be identified 1 1 1 1 1 0 0 device id address acknowledge from slave to be identified a m3 m2 m1 m0 acknowledge from master manufacturer name = 000000000000 p8 p7 p6 p5 a acknowledge from master p4 p3 p2 p1 p0 r2 r1 r0 part identification = 100001010 revision = 000 fig 10. control register 002aab190 x x x x b3 b2 b1 b0 channel selection bits (read/write) 76543210 channel 0 channel 1 channel 2 channel 3
pca9846 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015. all rights res erved. product data sheet rev. 1 ? 9 november 2015 10 of 32 nxp semiconductors pca9846 4-channel ultra-low voltage, fm+ i 2 c-bus switch with reset 6.3.1 control register definition a scx/sdx downstream pair, or channel, is selected by the contents of the control register. this register is written after the pca9846 has been addressed. all 8 bits of the control byte are used to determine which channel or channels are to be selected. when a channel is selected, it will be come active after a stop co ndition has been placed on the i 2 c-bus. this ensures that all scx/sdx lines will be in a high state when the channel is made active, so that no false conditions are generated at the time of connection. notice that multiple channels may simultaneously be selected. remark: several channels can be enabled at the same time. example: b3 = 0, b2 = 1, b1 = 1, b0 = 0, means that channel 0 and channel 3 are disabled and channel 1 and channel 2 are enabled. care should be taken not to exceed the maximum bus capacitance. 6.4 reset input the reset input is an active low signal which may be used to recover from a bus fault condition. by asserting this signal low for a minimum of t w(rst)l , the pca9846 will reset its registers and i 2 c-bus state machine and w ill deselect all channels. 6.5 power-on reset when power is applied to v dd , an internal power-on reset (por) holds the pca9846 in a reset condition until v dd2 has reached v por . at this point, the reset condition is released and the pca9846 registers and i 2 c-bus state machine are initializ ed to their default states (all zeroes) causing all the channels to be deselected. 6.6 power-on reset requirements in the event of a glitch or data corruption, pc a9846 can be reset to its default conditions by using the power-on reset feature. power-on reset requires that the device go through a power cycle to be complete ly reset. this reset also happens when the device is powered on for the first time in an application. power-on reset is shown in figure 11 . table 5. control register write = channel selection; read = channel status d7 d6 d5 d4 b3 b2 b1 b0 command xxxxxxx 0 channel 0 disabled 1 channel 0 enabled xxxxxx 0 x channel 1 disabled 1 channel 1 enabled xxxxx 0 xx channel 2 disabled 1 channel 2 enabled xxxx 0 xxx channel 3 disabled 1 channel 3 enabled 0 0 0 0 0 0 0 0 no channel selected; power-up/reset default state
pca9846 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015. all rights res erved. product data sheet rev. 1 ? 9 november 2015 11 of 32 nxp semiconductors pca9846 4-channel ultra-low voltage, fm+ i 2 c-bus switch with reset ta b l e 6 specifies the performance of the power-on reset feature for pca9846 for both types of power-on reset. [1] level that v dd2 can glitch down to with a ramp rate = 0.4 ? s/v, but not cause a functional disruption when t w(gl)vdd <1 ? s. [2] glitch width that will not cause a functional disruption when ? v dd(gl) =0.5 ? v dd2 . glitches in the power supply can also affect the power-on reset performance of this device. the glitch width (t w(gl)vdd ) and glitch height ( ? v dd(gl) ) are dependent on each other. the bypass capacitance, source impedan ce, and device impedance are factors that affect power-on reset performance. figure 12 and ta b l e 6 provide more information on how to measure thes e specifications. v por is critical to the power-on reset. v por is the voltage level at which the reset condition is released and all the registers and the i 2 c-bus/smbus state machine are initialized to their default states. the value of v por differs based on the v dd2 being lowered to or from 0v. figure 13 and ta b l e 6 provide more details on this specification. fig 11. v dd2 is lowered below the por threshol d, then ramped back up to v dd2 aaa-014361 v dd2 time ramp-down (dv/dt) f ramp-up (dv/dt) r time to re-ramp when v dd2 drops to v por(min) ? 50 mv or below 0.2 v to v ss t d(rst) v i drops below por levels table 6. recommended supply seuencing and ramp rates t amb =25 ? c (unless otherwise noted). not tested; specified by design. symbol parameter condition min typ max unit (dv/dt) f fall rate of change of voltage figure 11 0.1 - 2000 ms (dv/dt) r rise rate of change of voltage figure 11 0.1 - 2000 ms t d(rst) reset delay time figure 11 ; re-ramp time when v dd2 drops to v por(min) ? 50 mv) or below 0.2 v to v ss 1- - ? s ? v dd(gl) glitch supply voltage difference figure 12 [1] --1.0v t w(gl)vdd supply voltage glitch pulse width figure 12 [2] --10 ? s v por(trip) power-on reset trip voltage falling v dd2 0.7 - - v rising v dd2 --1.5v fig 12. glitch width and glitch height aaa-014362 v dd2 time t w(gl)vdd ?v dd(gl)
pca9846 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015. all rights res erved. product data sheet rev. 1 ? 9 november 2015 12 of 32 nxp semiconductors pca9846 4-channel ultra-low voltage, fm+ i 2 c-bus switch with reset fig 13. power-on reset voltage (v por ) aaa-014363 por time v dd2 time v por (rising v dd2 ) v por (falling v dd2 )
pca9846 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015. all rights res erved. product data sheet rev. 1 ? 9 november 2015 13 of 32 nxp semiconductors pca9846 4-channel ultra-low voltage, fm+ i 2 c-bus switch with reset 6.7 voltage level translation between i 2 c-buses today?s complex systems often use multiple power supplies to maximize power savings and to meet the operating specifications of the devices used. this means that various i 2 c-buses are also operating at differing voltage levels and cannot simply connect together. in addition, modern microcontrollers operate down to 0.8 v to save power, further complicating the connection of i 2 c-buses. the pca9846 is specifically designed to seamle ssly handle these voltage level translation issues. any combination of bus voltages can be intermixed on the pca9846 and correctly translated to the other bus at fm+ (1 mhz) speed. figure 14 shows a typical application. the microcontroller acts as the master and operates at 0.8 v with its i 2 c-bus swinging between 0 v and 0.8 v. the temperature sensor on channel 0 of the pca9846 has a operates at 3.3 v, while the gpio expander on channel 1 operates down to 1.8 v to interf ace with chip select and reset inputs on various other ics also operating at 1.8 v. channel 2 of the pca9846 is connected to the i 2 c-bus of a power management device, o perating at 2.5 v. the other channels of pca9846 are simply left unconnected. v dd1 of the pca9846 is a bias supply and is set at the lowest bus voltage, or 0.8 v of the microcontroller. v dd1 sets the input switching points of each scl and sda at 0.3 ? v dd1 for a low level and 0.7 ? v dd1 for a high level. v dd2 is the core logic supply from which most of the pca9846 circuitry runs. it must be at least 0.8 v larger than v dd1 to allow proper operation of the pass transistor switches. since v dd1 is 0.8 v, v dd2 must be greater than 1.6 v. since the gpio expander on channel 1 is running at 1.8 v, an ad equate power supply is available. the i 2 c-bus is open-drain, so pull-up resistors are needed on each i 2 c-bus segment. this is where the voltage level translation happens. the pass transistor internal to the pca9846 limit the output voltage to v dd1 which is the lowest bus voltage. the pull-up resistors will then limit the high level of ea ch bus segment to the power supply of the devices on that segment. note that the pull- up resistors on channel 0 are connected to 3.3 v, the and resistors on channel 1 are c onnected to 1.8 v, while the resistors on channel 2 are connected to 2.5 v ? effectivel y translating the 0.8 v signal swing of the microcontroller to the correct voltage level for each peripheral. one thing to note is noise margin on each i 2 c-bus segment is somewhat reduced due to the input levels set by v dd1 . especially in this example, the i 2 c-bus low level is 0.3 ? v dd1 or 0.24 v, so extreme care must be taken to ensure all bus segments meet this specification. it also means that static offset buffers may not work correctly if the offset side is connected to the pca9846. another point to examine is th at there is no buffering capa bility between the upstream and the downstream buses. this is simply a pass transistor, which acts like a switch and a series resistor, between these bus segm ents. the series resistance is the r on of the pass transistor and is inversely proportional to the minimum of v dd1 + v th or v dd2 , where v th is approximately 0.8 v. refer to ta b l e 8 for some representative r on values. an upcoming application note will explain r on more thoroughly. therefore, a careful analysis of bus capacitance and pull-up resi stor values is called for.
pca9846 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015. all rights res erved. product data sheet rev. 1 ? 9 november 2015 14 of 32 nxp semiconductors pca9846 4-channel ultra-low voltage, fm+ i 2 c-bus switch with reset a further point to consider is pull-up resistor selection. since mult iple channels can be simultaneously selected, the pull-up resistors on each channel are connected in parallel. ensure each device can correctly drive the effective pull-up resistor value and still meet the low-level specifications. fig 14. typical application for pca9846 with differing bus voltages pca9846 sc0 sd0 sda scl 1.8 v 0.8 v micro- controller aaa-017307 sda scl sc1 sd1 sc2 sd2 v dd2 0.8 v v dd1 3.3 v 3.3 v 1.8 v 1.8 v 2.5 v 2.5 v scl sda temp sensor 3.3 v scl sda gpio 1.8 v scl sda power mgmt controller 2.5 v v dd 0.8 v 0.8 v sc3 sd3 0.8 v to 3.6 v scl sda i 2 c-bus peripheral 0.8 v to 3.6 v
pca9846 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015. all rights res erved. product data sheet rev. 1 ? 9 november 2015 15 of 32 nxp semiconductors pca9846 4-channel ultra-low voltage, fm+ i 2 c-bus switch with reset 7. characteristics of the i 2 c-bus the pca9846 is an i 2 c slave device. data is exchanged between the master and the pca9846 through write and read commands conforming to the i 2 c-bus protocol. the two communication lines are scl (serial clock) and sda (serial data), both of which must be connected to v dd1 through pull-up resistors. 7.1 write commands data is transmitted to the pca9846 by send ing its device address and setting the least significant bit (lsb) to a logic 0 (see ta b l e 4 for device addresses), which the pca9846 acknowledges (ack). the control register byte is sent after the address that determines which downstream channel is connected to the upstream channel by bit 0 through bit 2. bit 7 through bit 3 are ignored and can be written with any data. there is no limit on the number of bytes sent after the address and before a stop condition, only the last byte written before the stop condition is recognized and the selected channel is enabled only at the following stop condition. 7.2 read commands data is read from the pca9846 by sending its device address and setting the least significant bit (lsb) to a logic 1 (see ta b l e 4 for device addresses), which the pca9846 acknowledges. the control register byte is read by the master with each byte either ack or nack by the master. if the master acks th e control register byte, it continues to send register data until the master nacks, signa ling the transaction is complete. there is no limit on the number of bytes read from the pca9846. the control register bit definitions are shown in figure 10 . bit 0 through bit 2 will show the enabled channels (as determined by the last write). refer to table 4 . fig 15. write control register aaa-019449 b7 b6 b5 b4 b3 b2 b1 b0 1/0 1 1/0 1/0 1/0 1/0 0 a s 1 a p slave address start condition r/w acknowledge from slave acknowledge from slave control register sda stop condition refer to table 4 . fig 16. read control register aaa-019450 b7 b6 b3 b2 b1 b0 1/0 1 1/0 1/0 1/0 1/0 1 a s 1 na p slave address start condition r/w acknowledge from slave no acknowledge from master control register sda stop condition last byte b5 b4
pca9846 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015. all rights res erved. product data sheet rev. 1 ? 9 november 2015 16 of 32 nxp semiconductors pca9846 4-channel ultra-low voltage, fm+ i 2 c-bus switch with reset 8. limiting values [1] the performance capability of a high-perfo rmance integrated circuit in conjunction with its thermal environment can create j unction temperatures which are detrimental to reliability. the maximum junction temperature of this integrated circuit should not excee d 125 ? c. 9. static characteristics table 7. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to v ss (ground=0v) [1] . symbol parameter conditions min max unit v dd supply voltage ? 0.5 +4.0 v v i input voltage ? 0.5 +4.0 v i i input current - ? 20 ma i o output current - ? 25 ma i dd supply current - ? 100 ma i ss ground supply current - ? 100 ma p tot total power dissipation - 400 mw t stg storage temperature ? 60 +150 ?c t amb ambient temperature operating ? 40 +85 ?c table 8. static characteristics v ss = 0 v; t amb = ? 40 ? c to +85 ? c; unless otherwise specified. symbol parameter conditions min typ max unit supply v dd1 supply voltage 1 0.8 - 3.6 v v dd2 supply voltage 2 1.65 - 3.6 v i dd(vdd2) supply current on pin v dd2 v dd1 =3.6v, v dd2 =3.6v; sc0tosc7 and sd0 to sd7 not connected; reset =v dd1 ; a0 = a1 = scl; continuous regi ster read/write f scl = 0 khz - 5 12 ? a f scl = 100 khz - 8 20 ? a f scl = 1000 khz - 65 150 ? a i dd(vdd1) supply current on pin v dd1 v dd1 =3.6v, v dd2 =3.6v; sc0tosc7 and sd0 to sd7 not connected; reset =v dd1 ; a0 = a1 = scl; continuous regi ster read/write f scl = 0 khz ? 5 ? 2+2 ? a f scl = 100 khz - 5 15 ? a f scl = 1000 khz - 45 100 ? a v por power-on reset voltage - 1.2 1.5 v
pca9846 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015. all rights res erved. product data sheet rev. 1 ? 9 november 2015 17 of 32 nxp semiconductors pca9846 4-channel ultra-low voltage, fm+ i 2 c-bus switch with reset [1] not tested in production. guaranteed by design and characterization. input scl; input/output sda v il low-level input voltage v dd1 ? 1.1 v ? 0.5 - +0.2v dd1 v v dd1 >1.1v ? 0.5 - +0.3v dd1 v v ih high-level input voltage v dd1 = ? 1.1 v 0.8v dd1 -3.6 v v dd1 > 1.1 v 0.7v dd1 -3.6 v i ol low-level output current v ol = 0.4 v; v dd2 ? 2v 15 - - ma v ol = 0.4 v; v dd2 >2v 20 - - ma i l leakage current v i =v dd or v ss ? 1-+1 ? a c i input capacitance v i =v ss ; all channels disabled [1] -2040pf select inputs a0 to a1, reset v il low-level input voltage v dd1 ? 1.1 v ? 0.5 - +0.2v dd1 v v dd1 >1.1v ? 0.5 - +0.3v dd1 v v ih high-level input voltage v dd1 ? 1.1 v 0.8v dd1 -3.6 v dd1 > 1.1 v 0.7v dd1 -3.6 v i li input leakage current pin at v dd2 to 3.6 v or v ss ? 1-+1 ? a c i input capacitance v i =v ss or v dd1 [1] -510pf pass gate r on on-state resistance on resist ance of the pass transistor between scl and scx, and sda and sdx v dd1 = 0.8 v; v dd2 ? 1.65 v; v i(sw) =0.16v; i o =3ma -1524 ? v dd1 = 1.2 v; v dd2 ? 1.8 v; v i(sw) =0.24v; i o =6ma -1218 ? v dd1 >2v; v dd2 ? 2.5 v; v i(sw) =0.4v;i o =20ma -710 ? i o(sw) switch output current v dd2 = 1.65 v to 3.6 v; v i(sw) =v dd1 to 3.6 v; v o(sw) =v dd1 to 3.6 v 0-100 ? a i l leakage current v i =v dd or v ss ? 1-+1 ? a c io input/output capacitance v i =v ss ; all switches disabled [1] -815pf table 8. static characteristics ?continued v ss = 0 v; t amb = ? 40 ? c to +85 ? c; unless otherwise specified. symbol parameter conditions min typ max unit
pca9846 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015. all rights res erved. product data sheet rev. 1 ? 9 november 2015 18 of 32 nxp semiconductors pca9846 4-channel ultra-low voltage, fm+ i 2 c-bus switch with reset r on = (v o(sw) ? (v i(sw) ) / i o ; v i(sw) and i o are defined in ta b l e 8 fig 17. r on test circuit sda or scl sdx or scx dut v i(sw) = 0.2 v dd1 measured v o(sw) v dd2 i o v dd1 aaa-015928
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x pca9846 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015. all rights res erved. product data sheet rev. 1 ? 9 november 2015 19 of 32 nxp semiconductors pca9846 4-channel ultra-low voltage, fm+ i 2 c-bus switch with reset 10. dynamic characteristics table 9. dynamic characteristics symbol parameter conditions standard-mode i 2 c-bus fast-mode i 2 c-bus fast-mode plus i 2 c-bus unit min max min max min max t pd propagation delay from sda to sdx, or scl to scx -1 [1] -1 [1] -1 [1] ns f scl scl clock frequency 0 100 0 400 0 1000 khz t buf bus free time between a stop and start condition 4.7 - 1.3 - 0.5 - ? s t hd;sta hold time (repeated) start condition [2] 4.0 - 0.6 - 0.26 - ? s t low low period of the scl clock 4.7 - 1.3 - 0.5 - ? s t high high period of the scl clock 4.0 - 0.6 - 0.26 - ? s t su;sta set-up time for a repeated start condition 4.7 - 0.6 - 0.26 - ? s t su;sto set-up time for stop condition 4.0 - 0.6 - 0.26 - ? s t hd;dat data hold time 0 [3] 3.45 0 [3] 0.9 0 - ? s t su;dat data set-up time 250 - 100 - 50 - ns t r rise time of both sda and scl signals - 1000 20 ? (v dd /5.5v) [4] 300 - 120 ns t f fall time of both sda and scl signals - 300 20 ? (v dd /5.5v) [4] 300 20 ? (v dd /5.5v) [4] 120 [5] ns c b capacitive load for each bus line - 400 - 400 - 550 pf t sp pulse width of spikes that must be suppressed by the input filter -50 - 50 0 50 [6] ns t vd;dat data valid time [7] - 3.45 - 0.9 - 0.45 ? s t vd;ack data valid acknowledge time - 1 - 1 - 0.45 [8] ? s reset t w(rst)l low-level reset time 100 - 100 - 100 - ns t rst reset time sda clear 500 - 500 - 500 - ns t rec;sta recovery time to start condition 0 - 0 - 0 - ns
pca9846 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015. all rights res erved. product data sheet rev. 1 ? 9 november 2015 20 of 32 nxp semiconductors pca9846 4-channel ultra-low voltage, fm+ i 2 c-bus switch with reset [1] pass gate propagation delay is calculated from the 20 ? typical r on and the 50 pf load capacitance. [2] after this period, the first clock pulse is generated. [3] a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ih(min) of the scl signal) in order to bridge the undefined region of the falling edge of scl. [4] necessary to be backwards compatible to fast-mode. [5] in fast-mode plus, fall time is specified the same for bot h output stage and bus timing. if se ries resistors are used, desig ners should allow for this when c onsidering bus timing. [6] input filters on the sda and scl inputs su ppress noise spikes of less than 50 ns. [7] measurements taken with 1 k ? pull-up resistor and 50 pf load. [8] the maximum t hd;dat could be 3.45 ? s and 0.9 ? s for standard-mode and fast-mode, but must be less than the maximum of t vd;dat or t vd;ack by a transition time. this maximum must only be met if the device does not stretch the low period (t low ) of the scl signal. if the clock stretches the scl, the data must be valid by the set-up time before it releases the clock. fig 18. definition of timing on the i 2 c-bus t sp t buf t hd;sta p p s t low t r t hd;dat t f t high t su;dat t su;sta sr t hd;sta t su;sto sda scl 002aaa986 0.7 v dd 0.3 v dd 0.7 v dd 0.3 v dd fig 19. definition of reset timing sda scl 002aac549 50 % 30 % 50 % 50 % t rec;sta t w(rst)l reset start t rst ack or read cycle
pca9846 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015. all rights res erved. product data sheet rev. 1 ? 9 november 2015 21 of 32 nxp semiconductors pca9846 4-channel ultra-low voltage, fm+ i 2 c-bus switch with reset rise and fall times refer to v il and v ih . fig 20. i 2 c-bus timing diagram 002aab175 protocol start condition (s) bit 7 msb (a7) bit 6 (a6) bit 0 (r/w) acknowledge (a) stop condition (p) scl sda t hd;sta t su;dat t hd;dat t f t buf t su;sta t low t high t vd;ack t su;sto 1 / f scl t r t vd;dat 0.3 v dd 0.7 v dd 0.3 v dd 0.7 v dd
pca9846 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015. all rights res erved. product data sheet rev. 1 ? 9 november 2015 22 of 32 nxp semiconductors pca9846 4-channel ultra-low voltage, fm+ i 2 c-bus switch with reset 11. package outline fig 21. package outline sot403-1 (tssop16) 81,7 $ $ $ e s f ' ( h + ( / / s 4 = \ z y 5()(5(1&(6 287/,1( 9(56,21 (8523($1 352-(&7,21 ,668('$7( ,(& -('(& -(,7$ pp r r ',0(16,216ppduhwkhruljlqdoglphqvlrqv 1rwhv 3odvwlfruphwdosurwuxvlrqvripppd[lpxpshuvlghduh qrwlqfoxghg 3odvwlflqwhuohdgsurwuxvlrqvripppd[lpxpshuvlghdu hqrwlqfoxghg 627 02 z 0 e s ' = h $ $ $ / s 4 ghwdlo; / $ + ( ( f y 0 $ ; $ \ pp vfdoh 76623sodvwlfwklqvkulqnvpdoorxwolqhsdfndjhohdgve rg\zlgwkpp 627 $ pd[ slqlqgh[
pca9846 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015. all rights res erved. product data sheet rev. 1 ? 9 november 2015 23 of 32 nxp semiconductors pca9846 4-channel ultra-low voltage, fm+ i 2 c-bus switch with reset fig 22. package outline sot629-1 (hvqfn16) whuplqdo lqgh[duhd $ ( k e 81,7 \ h f 5()(5(1&(6 287/,1( 9(56,21 (8523($1 352-(&7,21 ,668('$7( ,(& -('(& -(,7$ pp ' k \ h h ',0(16,216ppduhwkhruljlqdoglphqvlrqv 627 02 / y z pp vfdoh 627 +94)1sodvwlfwkhupdohqkdq fhgyhu\wklqtxdgiodwsdfndjh qrohdgv whuplqdoverg\[[pp $ pd[ $ $ f ghwdlo; \ \ & h / ( k ' k h h e ; ' ( & % $ h whuplqdo lqgh[duhd h h $ & & % y 0 z 0 ( 1rwh 3odvwlfruphwdosurwuxvlrqvripppd[lpxpshuvlghduhqrwlqfoxghg '
pca9846 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015. all rights res erved. product data sheet rev. 1 ? 9 november 2015 24 of 32 nxp semiconductors pca9846 4-channel ultra-low voltage, fm+ i 2 c-bus switch with reset 12. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 12.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 12.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 12.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities
pca9846 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015. all rights res erved. product data sheet rev. 1 ? 9 november 2015 25 of 32 nxp semiconductors pca9846 4-channel ultra-low voltage, fm+ i 2 c-bus switch with reset 12.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 23 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 1 0 and 11 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 23 . table 10. snpb eutectic process (from j-std-020d) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 11. lead-free process (from j-std-020d) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
pca9846 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015. all rights res erved. product data sheet rev. 1 ? 9 november 2015 26 of 32 nxp semiconductors pca9846 4-channel ultra-low voltage, fm+ i 2 c-bus switch with reset for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . msl: moisture sensitivity level fig 23. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature
pca9846 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015. all rights res erved. product data sheet rev. 1 ? 9 november 2015 27 of 32 nxp semiconductors pca9846 4-channel ultra-low voltage, fm+ i 2 c-bus switch with reset 13. soldering: pcb footprints fig 24. pcb footprint for sot403-1 (tssop16); reflow soldering ',0(16,216lqpp $\ %\ ' ' *\ +\ 3 & *[ vrwbiu +[ 627 vroghuodqg rffxslhgduhd )rrwsulqwlqirupdwlrqiruuhiorzvroghulqjri76623sdfndjh $\ %\ *\ & +\ +[ *[ 3 *hqhulfirrwsulqwsdwwhuq 5hihuwrwkhsdfndjhrxwolqhgudzlqjirudfwxdood\rxw 3 ' '[ 3
pca9846 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015. all rights res erved. product data sheet rev. 1 ? 9 november 2015 28 of 32 nxp semiconductors pca9846 4-channel ultra-low voltage, fm+ i 2 c-bus switch with reset fig 25. pcb footprint for sot629-1 (hvqfn16); reflow soldering 627 )rrwsulqwlqirupdwlrqiruuhiorzvroghulqjri+94)1sdfndjh 'lphqvlrqvlqpp $[ $\ %[ %\ ' 6/[ 6/\ 63[wrw 63\wrw 63[ 63\ *[ *\ +[ +\ 3 & q63[ q63\ vrwbiu rffxslhgduhd $[ %[ 6/[ *[ *\ +\ +[ $\%\6/\ 3 ' 63[wrw 63\wrw q63[ q63\ 63[ 63\ vroghuodqgsoxvvroghusdvwh vroghuodqg vroghusdvwhghsrvlw & *hqhulfirrwsulqwsdwwhuq 5hihuwrwkhsdfndjhrxwolqhgudzlqjirudfwxdood\rxw ,vvxhgdwh
pca9846 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015. all rights res erved. product data sheet rev. 1 ? 9 november 2015 29 of 32 nxp semiconductors pca9846 4-channel ultra-low voltage, fm+ i 2 c-bus switch with reset 14. abbreviations 15. revision history table 12. abbreviations acronym description cdm charged-device model cpu central processing unit esd electrostatic discharge fm+ fast-mode plus hbm human body model ic integrated circuit i 2 c-bus inter-integrated circuit bus lsb least significant bit msb most significant bit pcb printed-circuit board smbus system management bus table 13. revision history document id release date data sheet status change notice supersedes pca9846 v.1 20151109 product data sheet - -
pca9846 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015. all rights res erved. product data sheet rev. 1 ? 9 november 2015 30 of 32 nxp semiconductors pca9846 4-channel ultra-low voltage, fm+ i 2 c-bus switch with reset 16. legal information 16.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 16.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 16.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
pca9846 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015. all rights res erved. product data sheet rev. 1 ? 9 november 2015 31 of 32 nxp semiconductors pca9846 4-channel ultra-low voltage, fm+ i 2 c-bus switch with reset export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 16.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp semiconductors n.v. 17. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors pca9846 4-channel ultra-low voltage, fm+ i 2 c-bus switch with reset ? nxp semiconductors n.v. 2015. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 9 november 2015 document identifier: pca9846 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 18. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 functional description . . . . . . . . . . . . . . . . . . . 5 6.1 device address . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 software reset general call, and device id addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2.1 software reset . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2.2 device id (pca9846 id field) . . . . . . . . . . . . . . 8 6.3 control register . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.3.1 control register definition . . . . . . . . . . . . . . . . 10 6.4 reset input . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.5 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 10 6.6 power-on reset requirements . . . . . . . . . . . . . 10 6.7 voltage level translation between i 2 c-buses . 13 7 characteristics of the i 2 c-bus . . . . . . . . . . . . 15 7.1 write commands. . . . . . . . . . . . . . . . . . . . . . . 15 7.2 read commands . . . . . . . . . . . . . . . . . . . . . . 15 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 16 9 static characteristics. . . . . . . . . . . . . . . . . . . . 16 10 dynamic characteristics . . . . . . . . . . . . . . . . . 19 11 package outline . . . . . . . . . . . . . . . . . . . . . . . . 22 12 soldering of smd packages . . . . . . . . . . . . . . 24 12.1 introduction to soldering . . . . . . . . . . . . . . . . . 24 12.2 wave and reflow soldering . . . . . . . . . . . . . . . 24 12.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 24 12.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 25 13 soldering: pcb footprints. . . . . . . . . . . . . . . . 27 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 29 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . 29 16 legal information. . . . . . . . . . . . . . . . . . . . . . . 30 16.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 30 16.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 16.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 16.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 31 17 contact information. . . . . . . . . . . . . . . . . . . . . 31 18 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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